A semiconductor device disclosed in Japanese Patent Application Publication No, 2013-191734 has a MOSFET, and a plurality of termination trenches provided around the circumference of the MOSFET. Each of the termination trenches extends annularly so as to surround a region where the MOSFET is provided. Each of the termination trenches has an insulating layer disposed therein. Moreover, provided in a range of a semiconductor layer that is in contact with a bottom surface of each of the termination trenches is a p-type floating region. When the MOSFET is turned off, a depletion layer extends from a body region of the MOSFET toward an outer circumferential side (a region where the termination trenches are provided). When the depletion layer extends to the p-type floating region on a lower side of the innermost termination trench, the depletion layer further extends from that p-type floating region toward the outer circumferential side. When the depletion layer thereby extends to the next p-type floating region, the depletion layer further extends from that p-type floating region toward the outer circumferential side. As such, the depletion layer spreads widely, through each of the p-type floating regions, around the circumference of the region where the MOSFET is provided. The semiconductor device thereby achieves an improved withstand voltage.